A scannable storage circuit (e.g., a standard flip-flop, a scan flip-flop, etc.) may be a clocked digital circuit capable of serving as a one-bit memory. The standard flip-flop may be operated in two states (e.g., a zero state and a one state). The standard flip-flop may include a timing signal (e.g., controlled by a clock) and a data signal at an input to the standard flip-flop. When the timing signal is turned high, a stable data (e.g., data at the input before a set-up time of the standard flip-flop) may be transferred to an output of the standard flip-flop after a clock-to-Q delay of the standard flip-flop.
A synchronous-sequential circuit (a synchronous circuit in short) may be a digital circuit (e.g., an electronic circuit based on a number of discrete voltage levels) having sub-circuits that are synchronized (e.g., operated in unison) by flip-flops (e.g., may be used to coordinate actions of two or more sub-circuits). In the synchronous circuit, a timing signal (e.g., an external signal to generate a crystal oscillator and/or a timer etc.) may be used to simultaneously trigger a chain of standard flip-flops and other logic units (e.g., a combinational circuit).
The timing signal may oscillate between a high voltage and a low voltage and the standard flip-flop may transfer data between various sub-circuits of the synchronous circuit at either a rising edge and/or a falling edge of the timing signal. For proper operation of the synchronous circuit, propagation delays may be accounted for (e.g., a set up time, a clock-to-queue delay, etc.). The propagation delays may limit a maximum frequency (e.g., speed) of the synchronous circuit. Any stable data available at the input of each standard flip-flop one set-up time before a clock-edge hits the standard flip-flop, may be stably and/or reliably transferred to the output of the standard flip-flop after one clock-to-Q delay of the standard flip-flop.
The scan flip-flop may be a variation of the standard flip-flop designed to include additional testing circuitries and/or features. Therefore, the scan flip-flop can make it easier to validate that the synchronous circuit contains no defect that could adversely affect the synchronous circuit's correct functioning. An objective of the scan flip-flop may be to make testing easier by providing a way to precisely set inputs to known values and observe the output of every scan flip-flop in the synchronous circuit.
As such, a special signal called a scan enable signal may be added to each scan flip-flop in the synchronous circuit. When the scan enable signal is asserted, an arbitrary pattern can be entered into each scan flip-flop in the synchronous circuit from an alternate input signal (e.g., a test input ‘TI’), and a state of every scan flip-flop can be read out from the output (e.g., an alternate output ‘TO’). When the scan enable signal is not asserted, the stable data from the standard input may be transferred to the output of the scan flip-flop.
The scan flip-flop can bring an additional delay as compared to the standard flip-flop because of added circuitry used to provide the scan enable signal to the scan flip-flop. When the scan enable signal is asserted, data available at the alternate input signal may be transferred to the output on a next clock edge.
Even when the scan flip-flop is not asserted, the additional delay can hamper performance because data bits may have to pass through additional circuitry of the scan flip-flop. This delay may reduce the maximum operating frequency of the synchronous circuit because the set-up time in the scan flop may be increased (as compared to the standard flip-flop), and therefore the stable data may need to arrive earlier to be transferable by the scan flip-flop.